The present invention relates to a level shifter and more particularly to a CMOS level shifter.
Level shifters are well known in logic circuitry. Some prior art level shifters require current to flow between the positive and negative supply rails in one or both of the logic states. This can be avoided by use of CMOS technology but there then may be a problem in that the relative current sourcing/sinking ability of the NMOS and PMOS transistors may have to be balanced. This is problematical because of process tolerances.
It is accordingly an object of the present invention to at least partially mitigate the above-mentioned difficulties.
According to a first aspect of the present invention there is provided a level shifter comprising a current mirror having a circuit node for receiving a current controlled by a control current applied at a control node thereof, said current mirror being selectively connected to a supply terminal via a supply switch, the level shifter further comprising a first switch connected to said control node for selectively applying said control current in response to an input logic signal at an input node, a second switch for selectively pulling down said circuit node in response to said input logic signal and connecting circuitry connecting said circuit node to a control terminal of said supply switch.
Preferably supply switch is implemented in PMOS technology and said first and second switches are NMOS transistors.
According to a second aspect of the invention there is provided a level shifter comprising a current mirror having a circuit node for receiving a current controlled by a control current applied at a control node thereof, said current mirror being selectively connected to a supply terminal via a PMOS supply switch, the level shifter further comprising a first NMOS switch connected to said control node for selectively applying said control current in response to an input logic signal at an input node, a second NMOS switch for selectively pulling down said circuit node in response to said input logic signal and connecting circuitry connecting said circuit node to a control terminal of said supply switch, wherein said current mirror comprises first and second transistors having common drain/source terminals, the first transistor having a source/drain terminal in common with its gate terminal as said control node, and the second transistor having a gate terminal in common with the gate terminal of the first transistor and a source/drain terminal as said circuit node.
Advantageously said current mirror comprises first and second p transistors having common drain/source terminals, the first transistor having a source/drain terminal in common with its gate terminal as said control node, and the second transistor having a gate terminal in common with the gate terminal of the first transistor and a source/drain terminal as said circuit node.
Preferably said connecting circuitry includes pull-up circuitry connected to said circuit node for maintaining said circuit node potential when said supply switch disconnects said current mirror from said supply node.
Preferably said pull-up circuitry comprises a p FET.
In one embodiment said connecting circuitry further comprises a direct connection between said circuit node and a control node of said supply switch.
Alternatively said connecting circuitry comprises a first inverter connected between said circuit node and a gate of said pull-up FET and a second inverter connected between said gate of said pull-up FET and the control terminal of said supply switch.
Preferably said level shifter further comprises an input inverter connected between a control node of said first switch and a control node of said second switch.